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Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.

, , , and . IEEE Trans. Parallel Distrib. Syst., 29 (9): 2105-2120 (2018)

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Battery aware tasks allocating algorithm for multi-battery operated system., , , and . APCCAS, page 875-878. IEEE, (2010)An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications., , , , , , and . CICC, page 1-4. IEEE, (2013)Extending lifetime of battery-powered coarse-grained reconfigurable computing platforms., , , and . DATE, page 1-6. European Design and Automation Association, (2014)CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache., , , , and . IEEE Trans. VLSI Syst., 24 (7): 2548-2561 (2016)Towards Efficient Compact Network Training on Edge-Devices., , , and . ISVLSI, page 61-67. IEEE, (2019)Constructing Concurrent Data Structures on FPGA with Channels., , , , and . FPGA, page 172-177. ACM, (2019)A Novel Composite Method to Accelerate Control Flow on Reconfigurable Architecture (Abstract Only)., , , , and . FPGA, page 270. ACM, (2015)An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS., , , , , , and . VLSI Circuits, page 37-38. IEEE, (2018)Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation., , , , , , and . ISSCC, page 394-396. IEEE, (2019)A novel approach using a minimum cost maximum flow algorithm for fault-tolerant topology reconfiguration in NoC architectures., , , , , and . ASP-DAC, page 48-53. IEEE, (2015)