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Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.

, , , and . IEEE Trans. Parallel Distrib. Syst., 29 (9): 2105-2120 (2018)

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Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration., , , and . IEEE Trans. Parallel Distrib. Syst., 29 (9): 2105-2120 (2018)Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect., , and . DAC, page 40:1-40:6. ACM, (2017)Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (9): 1475-1488 (2016)