PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Wei, Shaojun"

Author of the publication

copydeleteadd this publication to your clipboard
A Flexible Energy- and Reliability-Aware Application Mapping for NoC-Based Reconfigurable Architectures.

, , , , , , and . IEEE Trans. VLSI Syst., 23 (11): 2566-2580 (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Wei Yu University of Stuttgart

Li-Wei Chen University of Stuttgart

Felix Weitbrecht University of Stuttgart

Daniel Weiskopf

Stefanie Weidner

 

Other publications of authors with the same name

Affine transformations for communication and reconfiguration optimization of loops on CGRAs., , , and . ISCAS, page 2541-2544. IEEE, (2013)A power-efficient network-on-chip for multi-core stream processors., , , and . ASICON, page 1-4. IEEE, (2013)Acceleration of Nested Conditionals on CGRAs via Trigger Scheme., , , and . ICCAD, page 597-604. IEEE, (2015)Joint affine transformation and loop pipelining for mapping nested loop on CGRAs., , , , and . DATE, page 115-120. ACM, (2015)Reconfigurable computing - evolution of Von Neumann architecture.. FPT, IEEE, (2010)An Efficient Hardware Random Number Generator Based on the MT Method., , , , and . CIT, page 1011-1015. IEEE Computer Society, (2012)Battery-Aware Variable Voltage Scheduling on Real-Time Multiprocessor Platforms., , , and . ISCAS, page 1883-1886. IEEE, (2007)TLIA: Efficient Reconfigurable Architecture for Control-Intensive Kernels with Triggered-Long-Instructions., , , , , and . IEEE Trans. Parallel Distrib. Syst., 27 (7): 2143-2154 (2016)Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures., , , , and . IEEE Trans. VLSI Syst., 24 (5): 1895-1908 (2016)Exploiting Parallelism of Imperfect Nested Loops on Coarse-Grained Reconfigurable Architectures., , , and . IEEE Trans. Parallel Distrib. Syst., 27 (11): 3199-3213 (2016)