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Disambiguation of "Drechsler, Rolf"

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SAT-Lancer: A Hardware SAT-Solver for Self-Verification.

, , , and . ACM Great Lakes Symposium on VLSI, page 479-482. ACM, (2018)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

PD Dr. Rolf Brack University of Stuttgart

Rolf Beißwanger University of Stuttgart

PD Dr. Michael Rolf Schweikert University of Stuttgart

Dr. -Ing. Rolf Stierle University of Stuttgart

Dr. Rolf Bauer University of Stuttgart

 

Other publications of authors with the same name

RevKit: A Toolkit for Reversible Circuit Design., , , and . Multiple-Valued Logic and Soft Computing, 18 (1): 55-65 (2012)Exact Synthesis of Elementary Quantum Gate Circuits., , , and . Multiple-Valued Logic and Soft Computing, 15 (4): 283-300 (2009)Heuristic Learning Based on Genetic Programming., , , and . Genetic Programming and Evolvable Machines, 3 (4): 363-388 (2002)Binary Decision Diagrams - Theory and Implementation., and . Springer, (1998)Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld (Equivalence Checking of Digital Circuits in an Industrial Environment).. it+ti - Informationstechnik und Technische Informatik, 43 (4): 200-205 (2001)Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits)., , , and . it - Information Technology, 52 (4): 216-223 (2010)Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques., , , and . FDL, page 146-151. ECSI, (2007)Efficient minimization of fully testable 2-SPP networks., , , and . DATE, page 1300-1305. European Design and Automation Association, Leuven, Belgium, (2006)Automatic design of low-power encoders using reversible circuit synthesis., , , and . DATE, page 1036-1041. IEEE, (2012)Panel: Future SoC verification methodology: UVM evolution or revolution?, , , , , , and . DATE, page 1-5. European Design and Automation Association, (2014)