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Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques.

, , , and . FDL, page 146-151. ECSI, (2007)

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Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld (Equivalence Checking of Digital Circuits in an Industrial Environment).. it+ti - Informationstechnik und Technische Informatik, 43 (4): 200-205 (2001)Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits)., , , and . it - Information Technology, 52 (4): 216-223 (2010)Binary Decision Diagrams - Theory and Implementation., and . Springer, (1998)Integrating observability don't cares in all-solution SAT solvers., , and . ISCAS, IEEE, (2006)Towards Formal Verification on the System Level.. IEEE International Workshop on Rapid System Prototyping, page 2-5. IEEE Computer Society, (2004)Ordered Kronecker functional decision diagrams und ihre Anwendung.. Goethe University Frankfurt am Main, (1996)Efficiency of Multi-Valued Encoding in SAT-based ATPG., , and . ISMVL, page 25. IEEE Computer Society, (2006)Grouping heuristics for word-level decision diagrams., , and . ISCAS (1), page 411-414. IEEE, (1999)Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques., , and . ISMVL, page 361-366. IEEE Computer Society, (2003)Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions., , and . ISMVL, page 95-101. IEEE Computer Society, (1998)