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Disambiguation of "Sülflow, André"

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Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits).

, , , and . it - Information Technology, 52 (4): 216-223 (2010)

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André Jaquemod University of Stuttgart

Univ. -Prof. Dr. rer. nat. André Thess University of Stuttgart

Dr. -Ing. André Müller University of Stuttgart

Dr. -Ing. André Buchau University of Stuttgart

André Weiß University of Stuttgart

 

Other publications of authors with the same name

Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits)., , , and . it - Information Technology, 52 (4): 216-223 (2010)Latency Analysis for Sequential Circuits., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (4): 643-647 (2014)RobuCheck: A Robustness Checker for Digital Circuits., , , and . DSD, page 226-231. IEEE Computer Society, (2010)Computing bounds for fault tolerance using formal techniques., , and . DAC, page 190-195. ACM, (2009)Latency Analysis for Sequential Circuits., , and . European Test Symposium, page 129-134. IEEE Computer Society, (2011)WoLFram- A Word Level Framework for Formal Verification., , , , and . IEEE International Workshop on Rapid System Prototyping, page 11-17. IEEE Computer Society, (2009)Using unsatisfiable cores to debug multiple design errors., , , and . ACM Great Lakes Symposium on VLSI, page 77-82. ACM, (2008)Robust Multi-Objective Optimization in High Dimensional Spaces., , and . EMO, volume 4403 of Lecture Notes in Computer Science, page 715-726. Springer, (2006)Automated Design Debugging in a Testbench-Based Verification Environment., , and . DSD, page 479-486. IEEE Computer Society, (2011)Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation., , and . ATS, page 145-150. IEEE Computer Society, (2015)