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Disambiguation of "De, Vivek"

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Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.

, , , and . IEEE Trans. VLSI Syst., 11 (3): 514-522 (2003)

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Nithyasree Vivekanandham Pushpalatha University of Stuttgart

Jörg Desel

Das ist Informatik (Eds.) Springer, (2001)

Univ. -Prof. Dr. Gerd de Bruyn University of Stuttgart

Anda Degeratu University of Stuttgart

Daniel Del Gaudio University of Stuttgart

 

Other publications of authors with the same name

Serial-Link Bus: A Low-Power On-Chip Bus Architecture., , , , and . IEEE Trans. on Circuits and Systems, 56-I (9): 2020-2032 (2009)Impact of Parameter Variations on Circuits and Microarchitecture., , , , , , and . IEEE Micro, 26 (6): 30-39 (2006)Introduction to the Special Issue on the 2011 Symposium on VLSI Circuits., and . J. Solid-State Circuits, 47 (4): 795-796 (2012)PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction., , , , , , , , and . ISSCC, page 352-353. IEEE, (2010)A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS., , , , , , , , , and 11 other author(s). ISSCC, page 66-68. IEEE, (2012)Analytical Model for the Propagation Delay of Through Silicon Vias., , , , and . ISQED, page 553-556. IEEE Computer Society, (2008)Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS., , , , , and . CICC, page 1-4. IEEE, (2014)Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS., , , , , , , , and . CICC, page 1-4. IEEE, (2014)A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS., , , and . ICCD, page 567-573. IEEE Computer Society, (2005)F1: Designing secure systems: Manufacturing, circuits and architectures., , , , , , and . ISSCC, page 492-494. IEEE, (2016)