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Disambiguation of "Ravichandran, Krishnan"

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Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS.

, , , , , and . CICC, page 1-4. IEEE, (2014)

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Dr. Ranjith Ravichandran University of Stuttgart

 

Other publications of authors with the same name

8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating., , , , , , , , and . ISSCC, page 152-153. IEEE, (2016)A Highly Efficient Reconfigurable Charge Pump Energy Harvester With Wide Harvesting Range and Two-Dimensional MPPT for Internet of Things., , , and . J. Solid-State Circuits, 51 (5): 1302-1312 (2016)A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response., , , , , , , and . VLSI Circuits, page 124-. IEEE, (2019)8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation., , , , , , , , , and 2 other author(s). ISSCC, page 1-3. IEEE, (2015)A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS., , , , , , , and . J. Solid-State Circuits, 53 (4): 1038-1048 (2018)A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS., , , , , , , , , and . CICC, page 1-4. IEEE, (2015)A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures., , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2020)Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS., , , , , and . J. Solid-State Circuits, 50 (8): 1809-1819 (2015)Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator., , , , , , , , , and 2 other author(s). J. Solid-State Circuits, 51 (1): 18-30 (2016)