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A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures.

R. Kumar, X. Liu, V. Suresh, H. Krishnamurthy, M. Anders, H. Kaul, K. Ravichandran, V. De, and S. Mathew. VLSI Circuits, page 1-2. IEEE, (2020)

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A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS.H. Krishnamurthy, V. Vaidya, P. Kumar, G. Matthew, S. Weng, B. Thiruvengadam, W. Proefrock, K. Ravichandran, and V. De. VLSIC, page 1-2. IEEE, (2014)A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS.P. Kumar, V. Vaidya, H. Krishnamurthy, S. Kim, G. Matthew, S. Weng, B. Thiruvengadam, W. Proefrock, K. Ravichandran, and V. De. CICC, page 1-4. IEEE, (2015)A SCA-Resistant AES Engine in 14nm CMOS with Time/Frequency-Domain Leakage Suppression using Non-Linear Digital LDO Cascaded with Arithmetic Countermeasures.R. Kumar, X. Liu, V. Suresh, H. Krishnamurthy, M. Anders, H. Kaul, K. Ravichandran, V. De, and S. Mathew. VLSI Circuits, page 1-2. IEEE, (2020)A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes.S. Kim, V. Vaidya, C. Schaef, A. Lines, H. Krishnamurthy, S. Weng, X. Liu, D. Kurian, T. Karnik, K. Ravichandran and 2 other author(s). VLSI Circuits, page 195-196. IEEE, (2018)Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities.S. Vangal, S. Paul, S. Hsu, A. Agarwal, S. Kumar, R. Krishnamurthy, H. Krishnamurthy, J. Tschanz, V. De, and C. Kim. IEEE Trans. Very Large Scale Integr. Syst., 29 (5): 843-856 (2021)A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation.C. Schaef, N. Desai, H. Krishnamurthy, S. Weng, H. Do, W. Lambert, K. Radhakrishnan, K. Ravichandran, J. Tschanz, and V. De. ISSCC, page 154-156. IEEE, (2019)Synthesizable delay line architectures for digitally controlled voltage regulators.O. Haridy, H. Krishnamurthy, A. Helmy, and Y. Ismail. SoCC, page 72-77. IEEE, (2012)A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS.H. Krishnamurthy, S. Weng, G. Matthew, N. Desai, R. Saraswat, K. Ravichandran, J. Tschanz, and V. De. J. Solid-State Circuits, 53 (4): 1038-1048 (2018)Reduction of Torque Ripple in Induction Motor Drives Using an Advanced Hybrid PWM Technique.K. Basu, J. Prasad, G. Narayanan, H. Krishnamurthy, and R. Ayyanar. IEEE Trans. Industrial Electronics, 57 (6): 2085-2091 (2010)A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response.K. Ahmed, H. Krishnamurthy, C. Augustine, X. Liu, S. Weng, K. Ravichandran, J. Tschanz, and V. De. VLSI Circuits, page 124-. IEEE, (2019)