Author of the publication

Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations.

, , and . ICCAD, page 900-907. IEEE Computer Society / ACM, (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 27 (3): 481-494 (2008)Derivation of signal flow for switch-level simulation., , , and . EURO-DAC, page 301-305. IEEE Computer Society, (1990)Bus encoding for total power reduction using a leakage-aware buffer configuration., , , and . IEEE Trans. VLSI Syst., 13 (12): 1376-1383 (2005)Design and Evaluation of Confidence-Driven Error-Resilient Systems., , , and . IEEE Trans. VLSI Syst., 22 (8): 1727-1737 (2014)Gate oxide leakage current analysis and reduction for VLSI circuits., , and . IEEE Trans. VLSI Syst., 12 (2): 155-166 (2004)Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices., , , , , and . IEEE Trans. VLSI Syst., 25 (3): 907-918 (2017)Yield-Driven Near-Threshold SRAM Design., , , and . IEEE Trans. VLSI Syst., 18 (11): 1590-1598 (2010)Leakage Current: Moore's Law Meets Static Power., , , , , , , , and . IEEE Computer, 36 (12): 68-75 (2003)Hierarchical analysis of power distribution networks., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 21 (2): 159-168 (2002)Modeling and analysis of crosstalk noise in coupled RLC interconnects., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (5): 892-901 (2006)