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Disambiguation of "Marinissen, Erik Jan"

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Application of deterministic logic BIST on industrial circuits.

, , , and . ITC, page 105-114. IEEE Computer Society, (2000)

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Erik Eppinger University of Stuttgart

Erik Hesselmeier University of Stuttgart

Tim Janz University of Stuttgart

PD Dr. phil. Frank Janle University of Stuttgart

Benedikt Janny

 

Other publications of authors with the same name

Robust Optimization of Test-Access Architectures Under Realistic Scenarios., , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 34 (11): 1873-1884 (2015)Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption., , , and . IEEE Trans. Computers, 64 (12): 3335-3347 (2015)Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip., , and . IEEE Trans. Computers, 52 (12): 1619-1632 (2003)Murphy goes 3D.. ISVLSI, page 102. IEEE Computer Socity, (2013)Contactless testing: Possibility or pipe-dream?, , , , , , and . DATE, page 676-681. IEEE, (2009)Efficient Wrapper/TAM Co-Optimization for Large SOCs., , and . DATE, page 491-498. IEEE Computer Society, (2002)A structured and scalable test access architecture for TSV-based 3D stacked ICs., , and . VTS, page 269-274. IEEE Computer Society, (2010)Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base., , , and . Asian Test Symposium, page 451-456. IEEE Computer Society, (2011)Test Cost Analysis for 3D Die-to-Wafer Stacking., , , and . Asian Test Symposium, page 435-441. IEEE Computer Society, (2010)Impact of 3D design choices on manufacturing cost., , , , and . 3DIC, page 1-5. IEEE, (2009)