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Disambiguation of "Leduc, Patrick"

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An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling.

, , , , , , , , , , , , , , and . 3DIC, page 1-4. IEEE, (2009)

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Patrick Gralka University of Stuttgart

Patrick Maisenhölder University of Stuttgart

Patrick Lerge University of Stuttgart

Patrick Hippold University of Stuttgart

Patrick Mesmer University of Stuttgart

 

Other publications of authors with the same name

Panel: "will 3D-IC remain a technology of the future... even in the future?"., , , , , , , and . DATE, page 1526-1530. EDA Consortium San Jose, CA, USA / ACM DL, (2013)A successful implementation of dual damascene architecture to copper TSV for 3D high density applications., , , , , , and . 3DIC, page 1-4. IEEE, (2010)First integration of Cu TSV using die-to-wafer direct bonding and planarization., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits., , , , , , , , and . 3DIC, page 1-8. IEEE, (2013)Which interconnects for which 3D applications? Status and perspectives., , , , , and . 3DIC, page 1-6. IEEE, (2013)Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric., , , , , , , , , and . Microelectronics Reliability, 53 (1): 17-29 (2013)An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling., , , , , , , , , and 5 other author(s). 3DIC, page 1-4. IEEE, (2009)Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits., , , , , , , , , and 3 other author(s). 3DIC, page 1-7. IEEE, (2009)