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Disambiguation of "Valentian, Alexandre"

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Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits.

, , , , , , , , , , , , and . 3DIC, page 1-7. IEEE, (2009)

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Alexandre Waquet University of Stuttgart

 

Other publications of authors with the same name

Modeling subthreshold SOI logic for static timing analysis., , , and . IEEE Trans. VLSI Syst., 12 (6): 662-669 (2004)Automatic Gate Biasing of an SCCMOS Power Switch Achieving Maximum Leakage Reduction and Lowering Leakage Current Variability., and . J. Solid-State Circuits, 43 (7): 1688-1698 (2008)Spiking Neural Networks Hardware Implementations and Challenges: A Survey., , , , , , and . JETC, 15 (2): 22:1-22:35 (2019)Advanced 3D Technologies and Architectures for 3D Smart Image Sensors., , , , , , , , , and 7 other author(s). DATE, page 674-679. IEEE, (2019)Experimental analysis of flip-flops minimum operating voltage in 28nm FDSOI and the impact of back bias and temperature., , , , and . PATMOS, page 1-7. IEEE, (2014)Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits., , , , , , , , , and 3 other author(s). 3DIC, page 1-7. IEEE, (2009)Limits of CMOS Technology and Interest of NEMS Relays for Adiabatic Logic Applications., , , , and . IEEE Trans. on Circuits and Systems, 62-I (6): 1546-1554 (2015)A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking., , , , , , , , , and 7 other author(s). J. Solid-State Circuits, 50 (1): 125-136 (2015)Automatic Power Regulation Based on an Asynchronous Activity Detection and its Application to ANOC Node Leakage Reduction., , , and . ASYNC, page 48-57. IEEE Computer Society, (2008)Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec., , , , , , , and . ISSCC, page 336-337. IEEE, (2011)