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An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling.

, , , , , , , , , , , , , , and . 3DIC, page 1-4. IEEE, (2009)

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An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling., , , , , , , , , and 5 other author(s). 3DIC, page 1-4. IEEE, (2009)First integration of Cu TSV using die-to-wafer direct bonding and planarization., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly., , , , , , , and . J. Solid-State Circuits, 42 (10): 2270-2282 (2007)Advances toward reliable high density Cu-Cu interconnects by Cu-SiO2 direct hybrid bonding., , , , , , , , , and . 3DIC, page 1-8. IEEE, (2014)200°C direct bonding copper interconnects : Electrical results and reliability., , , , , and . 3DIC, page 1-4. IEEE, (2011)Smart Stacking™ and Smart Cut™ technologies for wafer level 3D integration., , , and . ICICDT, page 231-234. IEEE, (2013)Novel low temperature 3D wafer stacking technology for high density device integration., , , , , , , , , and 1 other author(s). ESSDERC, page 151-154. IEEE, (2013)Impact of containment and deposition method on sub-micron chip-to-wafer self-assembly yield., , , , , and . 3DIC, page 1-5. IEEE, (2011)Recent Developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking., , , , , , , , , and 3 other author(s). 3DIC, page 1-6. IEEE, (2010)Chip to wafer copper direct bonding electrical characterization and thermal cycling., , , , , , , , and . 3DIC, page 1-7. IEEE, (2013)