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High speed pipelined ADCs: Fundamentals and variants.. CICC, page 1-145. IEEE, (2018)A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither., , , , , , , , , and 7 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter., , , , , , and . CICC, page 391-394. IEEE, (2005)A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 45 (12): 2602-2612 (2010)Correction of operational amplifier gain error in pipelined A/D converters., and . ISCAS (1), page 568-571. IEEE, (2001)Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC), , , , and . IEEE journal of solid state circuits, 57 (12): 3509-3513 (2022)A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration., , , , , , , , , and 4 other author(s). J. Solid-State Circuits, 49 (12): 2857-2867 (2014)A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration., , , , , , , , , and 3 other author(s). ISSCC, page 292-293. IEEE, (2010)