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Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)

W. Wu, H. Ito, J. Anders, A. Ali, and G. Pillonnet. IEEE journal of solid state circuits, 57 (12): 3509-3513 (2022)
DOI: 10.1109/JSSC.2022.3212205

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Hanchuan Wu University of Stuttgart

Yongxiang Wu University of Stuttgart

Tim Würtele University of Stuttgart

Amelie Wührl University of Stuttgart

PD Dr. phil. Joachim Wündisch University of Stuttgart

Other publications of authors with the same name

A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS.W. Wu, R. Staszewski, and J. Long. J. Solid-State Circuits, 49 (5): 1081-1096 (2014)Circuit technologies for mm-wave wireless systems on silicon.J. Long, Y. Zhao, Y. Jin, W. Wu, and M. Spirito. CICC, page 1-8. IEEE, (2011)Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)W. Wu, H. Ito, J. Anders, A. Ali, and G. Pillonnet. IEEE journal of solid state circuits, 57 (12): 3509-3513 (2022)9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation.R. Winoto, A. Olyaei, M. Hajirostam, W. Lau, X. Gao, A. Mitra, O. Carnu, P. Godoy, L. Tee, H. Li and 26 other author(s). ISSCC, page 170-171. IEEE, (2016)9.4 A 28nm CMOS digital fractional-N PLL with -245.5dB FOM and a frequency tripler for 802.11abgn/ac radio.X. Gao, L. Tee, W. Wu, K. Lee, A. Paramanandam, A. Jha, N. Liu, E. Chan, and L. Lin. ISSCC, page 1-3. IEEE, (2015)A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction.W. Wu, C. Yao, K. Godbole, R. Ni, P. Chiang, Y. Han, Y. Zuo, A. Verma, I. Lu, S. Son and 1 other author(s). J. Solid-State Circuits, 54 (5): 1254-1265 (2019)Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon.J. Long, Y. Zhao, W. Wu, M. Spirito, L. Vera, and E. Gordon. IEEE Trans. on Circuits and Systems, 59-I (8): 1680-1693 (2012)9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS.X. Gao, O. Burg, H. Wang, W. Wu, C. Tu, K. Manetakis, F. Zhang, L. Tee, M. Yayla, S. Xiang and 2 other author(s). ISSCC, page 174-175. IEEE, (2016)High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators.W. Wu, J. Long, and R. Staszewski. J. Solid-State Circuits, 48 (11): 2785-2794 (2013)17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks.W. Wu, M. Sanduleanu, X. Li, and J. Long. J. Solid-State Circuits, 43 (9): 1909-1919 (2008)