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Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors., , , , , and . Signal Processing Systems, 64 (1): 75-92 (2011)An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating., , , , , and . DSD, page 693-700. IEEE Computer Society, (2011)Memristor-Based (ReRAM) Data Memory Architecture in ASIP Design., , , , and . DSD, page 795-798. IEEE Computer Society, (2013)Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor., , , , and . VLSI Design, page 201-207. IEEE Computer Society, (2008)Novel energy-efficient scalable soft-output SSFE MIMO detector architectures., , , , , and . ICSAMOS, page 165-171. IEEE, (2009)Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures., , , , , , and . Integration, 41 (1): 38-48 (2008)Array Interleaving - An Energy-Efficient Data Layout Transformation., , , , and . ACM Trans. Design Autom. Electr. Syst., 20 (3): 44:1-44:26 (2015)Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors., , , , and . ACM Trans. Design Autom. Electr. Syst., 12 (4): 41 (2007)Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism., , , , and . PATMOS, volume 4148 of Lecture Notes in Computer Science, page 12-23. Springer, (2006)System-level assessment and area evaluation of Spin Wave logic circuits., , , , , , , and . NANOARCH, page 25-30. IEEE Computer Society/ACM, (2014)