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Locality and Balance for Communication-Aware Thread Mapping in Multicore Systems.

M. Diener, E. da Cruz, M. Alves, M. Alhakeem, P. Navaux, and H. Heiß. Euro-Par, volume 9233 of Lecture Notes in Computer Science, page 196-208. Springer, (2015)

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Dr. Astrid Diener University of Stuttgart

Matthias Keinert

Concept of a Computerized Numerical Control Kernel for Execution on Multi-core ProcessorsM. Keinert, A. Lechler, and A. Verl. IEEE Advanced Motion Control, page 599-604. (April 2016)

Concept of a Computerized Numerical Control Kernel for Execution on Multi-core ProcessorsM. Keinert, A. Lechler, and A. Verl. IEEE Advanced Motion Control, page 599-604. (April 2016)OPC UA Informationsmodell für CNC-Datenschnittstellen : standardisierte Schnittstelle für CNC-WerkzeugmaschinenM. Keinert, and A. Lechler. Automation 2015, 2258, page 593-604. Düsseldorf, VDI-Verl., (2015)Aufwertung von HMI-Systemen durch Design, Austauschbarkeit und IntelligenzM. Keinert, and P. Pruschek. (2013)

Matthias Bachmann

Matthias Bachmann

Matthias Bachmann

Other publications of authors with the same name

Modeling memory access behavior for data mapping.M. Diener, E. da Cruz, and P. Navaux. IJHPCA, 31 (3): 212-228 (2017)Exploring Instance Heterogeneity in Public Cloud Providers for HPC Applications.E. Roloff, M. Diener, L. Gaspary, and P. Navaux. CLOSER, page 210-222. SciTePress, (2019)Multi-Level Load Balancing with an Integrated Runtime Approach.S. Bak, H. Menon, S. White, M. Diener, and L. Kalé. CCGrid, page 31-40. IEEE Computer Society, (2018)Integrating OpenMP into the Charm++ Programming Model.S. Bak, H. Menon, S. White, M. Diener, and L. Kalé. ESPM2@SC, page 4:1-4:7. ACM, (2017)Using the Translation Lookaside Buffer to Map Threads in Parallel Applications Based on Shared Memory.E. da Cruz, M. Diener, and P. Navaux. IPDPS, page 532-543. IEEE Computer Society, (2012)Communication-Based Mapping Using Shared Pages.M. Diener, E. da Cruz, and P. Navaux. IPDPS, page 700-711. IEEE Computer Society, (2013)Performance Evaluation of Multiple Cloud Data Centers Allocations for HPC.E. Roloff, E. Carreño, J. Valverde-Sánchez, M. Diener, M. da Silva Serpa, G. Houzeaux, L. Schnorr, N. Maillard, L. Gaspary, and P. Navaux. CARLA, volume 697 of Communications in Computer and Information Science, page 18-32. (2016)Partial coscheduling of virtual machines based on memory access patterns.A. Busse, J. Schönherr, M. Diener, P. Navaux, and H. Heiß. SAC, page 2033-2038. ACM, (2015)Optimizing Memory Locality Using a Locality-Aware Page Table.E. da Cruz, M. Diener, M. Alves, L. Pilla, and P. Navaux. SBAC-PAD, page 198-205. IEEE Computer Society, (2014)Exploring Cache Size and Core Count Tradeoffs in Systems with Reduced Memory Access Latency.P. Santos, M. Alves, M. Diener, L. Carro, and P. Navaux. PDP, page 388-392. IEEE Computer Society, (2016)