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Evaluating the impact of customized instruction set on coarse grained reconfigurable arrays.

, , and . FPT, page 233-240. IEEE, (2008)

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Tuning Coarse-Grained Reconfigurable Architectures towards an Application Domain., , , , and . ReConFig, page 71-77. IEEE Computer Society, (2006)Evaluation and Design Methods for Processor-Like Reconfigurable Architectures., , , , and . Dynamically Reconfigurable Systems, Springer, (2010)Model-based Design of Self-adapting Networked Signal Processing Systems., , , and . SASO, page 41-50. IEEE Computer Society, (2013)Optimal Simultaneous Scheduling, Binding and Routing for Processor-Like Reconfigurable Architectures., , , , and . FPL, page 1-6. IEEE, (2006)Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures., , , , , and . FPT, page 381-384. IEEE, (2007)Model-Based Architecture Optimization for Self-Adaptive Networked Signal Processing Systems., , , and . SASO, page 187-188. IEEE Computer Society, (2014)Petri Net Based Interface Analysis for Fast IP-Core Integration., , and . MEMOCODE, page 34-. IEEE Computer Society, (2003)Coarse-grained reconfiguration., , , , , , , , , and 4 other author(s). FPL, page 349. IEEE, (2008)A Fast IP-Core Integration Methodology for SoC Design., , , , and . SBCCI, page 131-136. IEEE Computer Society, (2003)Charge Recycling in Voltage-Dithered Circuits., , , and . J. Low Power Electronics, 6 (2): 291-299 (2010)