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Disambiguation of "Polian, Ilia"

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Scenario-based Test Content Optimization: Scan Test vs. System-Level Test

, , , and . 2024 IEEE 42nd VLSI Test Symposium (VTS), page 1-7. Piscataway, NJ], IEEE, (2024)
DOI: 10.1109/VTS60656.2024.10538586

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Univ. -Prof. Dr. rer. nat. Ilia Polian University of Stuttgart

 

Other publications of authors with the same name

Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis., , , , , and . DDECS, page 15-20. IEEE Computer Society, (2006)Simulating Resistive Bridging and Stuck-At Faults., , , and . ITC, page 1051-1059. IEEE Computer Society, (2003)Power Supply Noise: Causes, Effects, and Testing.. J. Low Power Electronics, 6 (2): 326-338 (2010)Tomographic Testing and Validation of Probabilistic Circuits., , , and . European Test Symposium, page 63-68. IEEE Computer Society, (2011)Cross-Level Validation of Topological Quantum Circuits., , , and . RC, volume 8507 of Lecture Notes in Computer Science, page 189-200. Springer, (2014)A study of cognitive resilience in a JPEG compressor., , and . DSN, page 32-41. IEEE Computer Society, (2008)Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model., , , , , and . ITC, page 1-10. IEEE Computer Society, (2008)Multi-Stage Fault Attacks on Block Ciphers., , and . IACR Cryptology ePrint Archive, (2013)Special session 4B: Panel low-power test and noise-aware test: Foes or friends?. VTS, page 130. IEEE Computer Society, (2010)A Family of Logical Fault Models for Reversible Circuits., , , and . Asian Test Symposium, page 422-427. IEEE Computer Society, (2005)