PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Polian, Ilia"

Author of the publication

copydeleteadd this publication to your clipboard
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis.

, , , , , and . DDECS, page 15-20. IEEE Computer Society, (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Univ. -Prof. Dr. rer. nat. Ilia Polian University of Stuttgart

 

Other publications of authors with the same name

Power Supply Noise: Causes, Effects, and Testing.. J. Low Power Electronics, 6 (2): 326-338 (2010)Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths., , , , and . DATE, page 448-453. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Special session 4B: Panel low-power test and noise-aware test: Foes or friends?. VTS, page 130. IEEE Computer Society, (2010)Hardware security and test: Friends or enemies?. it - Information Technology, 56 (4): 192-202 (2014)Nichtstandardfehlermodelle für digitale Logikschaltkreise: Simulation, prüfgerechter Entwurf, industrielle Anwendungen (On Non-standard Fault Models for Logic Digital Circuits: Simulation, Design for Testability, Industrial Applications).. it - Information Technology, 47 (3): 172-174 (2005)A Family of Logical Fault Models for Reversible Circuits., , , and . Asian Test Symposium, page 422-427. IEEE Computer Society, (2005)Diagnosis of Realistic Defects Based on the X-Fault Model., , , , , , , and . DDECS, page 263-266. IEEE Computer Society, (2008)Fault-based attacks on cryptographic hardware., and . DDECS, page 12-17. IEEE Computer Society, (2013)Simulating Resistive Bridging and Stuck-At Faults., , , and . ITC, page 1051-1059. IEEE Computer Society, (2003)Tomographic Testing and Validation of Probabilistic Circuits., , , and . European Test Symposium, page 63-68. IEEE Computer Society, (2011)