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Disambiguation of "Wang, Po-Han"

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Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator.

, , , , , , , , , , , , , , , , , , and . ISPASS, page 127-128. IEEE Computer Society, (2017)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Liao Han University of Stuttgart

Qi Han

apl. Prof. Dr. -Ing. Niels Hansen University of Stuttgart

Replication Data for: Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis, and . Dataset, (2024)Related to: Schneider, Andreas; Lystbæk, Thomas B.; Markthaler, Daniel; Hansen, Niels; Hauer, Bernhard (2024): Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis. In: Nature Communications, 15, 4925. doi: 10.1038/s41467-024-48993-9.
Replication Data for: Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis, and . Dataset, (2024)Related to: Schneider, Andreas; Lystbæk, Thomas B.; Markthaler, Daniel; Hansen, Niels; Hauer, Bernhard (2024): Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis. In: Nature Communications, 15, 4925. doi: 10.1038/s41467-024-48993-9.Biocatalytic stereocontrolled head-to-tail cyclizations of unbiased terpenes as a tool in chemoenzymatic synthesis, , , , and . Nature Communications, 15 (1): 4925 (Jun 10, 2024)

Zhe Wang University of Stuttgart

Dr. Dongren Wang University of Stuttgart

 

Other publications of authors with the same name

PM-COSYN: PE and memory co-synthesis for MPSoCs., , and . DATE, page 1590-1595. IEEE, (2010)Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator., , , , , , , , , and 9 other author(s). ISPASS, page 127-128. IEEE Computer Society, (2017)Power gating strategies on GPUs., , , and . TACO, 8 (3): 13:1-13:25 (2011)Active forwarding: eliminate IOMMU address translation for accelerator-rich architectures., , and . DAC, page 112:1-112:6. ACM, (2018)Full system simulation framework for integrated CPU/GPU architecture., , , , , , , and . VLSI-DAT, page 1-4. IEEE, (2014)A Predictive Shutdown Technique for GPU Shader Processors., , , and . IEEE Comput. Archit. Lett., 8 (1): 9-12 (2009)A cycle-level SIMT-GPU simulation framework., , , and . ISPASS, page 114-115. IEEE Computer Society, (2012)Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling., , , and . IEEE Comput. Archit. Lett., 16 (2): 127-131 (2017)Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture., , and . DAC, page 5:1-5:6. ACM, (2016)A 220μW -85dBm Sensitivity BLE-Compliant Wake-up Receiver Achieving -60dB SIR via Single-Die Multi- Channel FBAR-Based Filtering and a 4-Dimentional Wake-Up Signature., and . ISSCC, page 440-442. IEEE, (2019)