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RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.

S. Shwe, K. Batra, Y. Yachide, J. Peddersen, and S. Parameswaran. ICCD, page 635-642. IEEE Computer Society, (2015)

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Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

Low-Impact Processor for Dynamic Runtime Power Management.J. Peddersen, and S. Parameswaran. IEEE Design & Test of Computers, 25 (1): 52-62 (2008)A simple digital architecture for a harmonic-cancelling sine-wave synthesizer.P. Aluthwala, N. Weste, A. Adams, T. Lehmann, and S. Parameswaran. ISCAS, page 2113-2116. IEEE, (2014)Dynamic reconfigurable puncturing for secure wireless communication.L. Tang, J. Ambrose, A. Kumar, and S. Parameswaran. DATE, page 888-891. ACM, (2015)Approximate Integer and Floating-Point Dividers with Near-Zero Error Bias.H. Saadat, H. Javaid, and S. Parameswaran. DAC, page 161. ACM, (2019)DRMA: dynamically reconfigurable MPSoC architecture.L. Zhang, J. Ambrose, J. Peddersen, S. Parameswaran, R. Ragel, S. Radhakrishnan, and K. Saluja. ACM Great Lakes Symposium on VLSI, page 239-244. ACM, (2013)ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective.I. Lu, N. Weste, and S. Parameswaran. VLSI Design, page 575-580. IEEE Computer Society, (2006)NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture.J. Chan, and S. Parameswaran. VLSI Design, page 717-720. IEEE Computer Society, (2004)Specification and Design of Multi-Million Gate SOCs.R. Chandra, P. Panda, J. Henkel, S. Parameswaran, and L. Ramachandran. VLSI Design, page 18-19. IEEE Computer Society, (2003)Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction.S. Min, J. Peddersen, and S. Parameswaran. VLSI Design, page 141-146. IEEE Computer Society, (2011)CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors.T. Li, M. Shafique, S. Rehman, S. Radhakrishnan, R. Ragel, J. Ambrose, J. Henkel, and S. Parameswaran. DATE, page 707-712. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Disambiguation of "Parameswaran, Sri"

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RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.

Please choose a person to relate this publication to

Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

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PUMA

Disambiguation of "Parameswaran, Sri"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.

Please choose a person to relate this publication to

Prashanth Srinivasan University of Stuttgart

Other publications of authors with the same name

Disambiguation

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URL
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APA
Chicago
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RAPITIMATE: Rapid performance estimation of pipelined processing systems containing shared memory.