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Disambiguation of "Murray, Brian T."

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Scalable Test Generators for High-Speed Datapath Circuits.

, , and . J. Electronic Testing, 12 (1-2): 111-125 (1998)

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T. Ertl

Dr. Brian Kagay University of Stuttgart

Brian Setz University of Stuttgart

T. Vietor

T. Maier

 

Other publications of authors with the same name

High-Level Test Generation for VLSI., , and . IEEE Computer, 22 (4): 16-24 (1989)Tolerating Transient Faults in Statically Scheduled Safety-Critical Embedded Systems., , and . SRDS, page 212-221. IEEE Computer Society, (1999)Built-in Test Pattern Generation For High-Performance Cir cuits Using Twisted-Ring Counters., , and . VTS, page 22-27. IEEE Computer Society, (1999)Hierarchical Test Generation Using Precomputed Tests for Modules., and . ITC, page 221-229. IEEE Computer Society, (1988)Test Width Compression for Built-In Self Testing., , , and . ITC, page 328-337. IEEE Computer Society, (1997)Providing convincing evidence of safety in X-by-wire automotive systems., , and . HASE, page 189-192. IEEE Computer Society, (2000)Design of built-in test generator circuits using width compression., and . IEEE Trans. on CAD of Integrated Circuits and Systems, 17 (10): 1044-1051 (1998)Optimal Space Compaction of Test Responses., , and . ITC, page 834-843. IEEE Computer Society, (1995)Time-Constrained Failure Diagnosis in Distributed Embedded Systems: Application to Actuator Diagnosis., , and . IEEE Trans. Parallel Distrib. Syst., 16 (3): 258-270 (2005)Deterministic Built-in Pattern Generation for Sequential Circuits., , and . J. Electronic Testing, 15 (1-2): 97-114 (1999)