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Design and validation of execution schemes for dynamically reconfigurable architectures.

, , and . FPT, page 353-356. IEEE, (2006)

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Spatial and Temporal Data Path Remapping for Fault-Tolerant Coarse-Grained Reconfigurable Architectures., , , , and . DFT, page 382-388. IEEE Computer Society, (2011)Evaluation and Design Methods for Processor-Like Reconfigurable Architectures., , , , and . Dynamically Reconfigurable Systems, Springer, (2010)Design and validation of execution schemes for dynamically reconfigurable architectures., , and . FPT, page 353-356. IEEE, (2006)Exploiting Slack Time in Dynamically Reconfigurable Processor Architectures., , , , , and . FPT, page 381-384. IEEE, (2007)Coarse-grained reconfiguration., , , , , , , , , and 4 other author(s). FPL, page 349. IEEE, (2008)Runtime-datapath-remapping for fault-tolerant coarse-grained reconfigurable architectures., , , , and . ReCoSoC, page 1-2. IEEE, (2011)Optimizing Partial Reconfiguration of Multi-context Architectures., , , and . ReConFig, page 67-72. IEEE Computer Society, (2008)Using Run-Time Reconfiguration to Implement Fault-Tolerant Coarse Grained Reconfigurable Architectures., , , , and . IPDPS Workshops, page 320-327. IEEE Computer Society, (2012)Optimization of Area and Performance by Processor-Like Reconfiguration., , and . IPDPS, page 1-8. IEEE, (2007)Vorausschauende Rekonfiguration dynamisch rekonfigurierbarer Prozessoren in einem System on Chip.. Eberhard Karls University of Tübingen, (2013)