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Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating., , , and . IEEE Trans. VLSI Syst., 15 (11): 1215-1224 (2007)Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (3): 468-479 (2007)A 150pW program-and-hold timer for ultra-low-power sensor platforms., , and . ISSCC, page 326-327. IEEE, (2009)Performance Driven OPC for Mask Cost Reduction., , , and . ISQED, page 270-275. IEEE Computer Society, (2005)Transition Aware Global Signaling (TAGS)., and . ISQED, page 53-59. IEEE Computer Society, (2002)Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (9): 1321-1334 (2011)Mechanical Stress Aware Optimization for Leakage Power Reduction., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 29 (5): 722-736 (2010)Statistical interconnect metrics for physical-design optimization., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (7): 1273-1288 (2006)Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits., , , , and . Proceedings of the IEEE, 98 (2): 253-266 (2010)Performance optimization of critical nets through active shielding., , and . IEEE Trans. on Circuits and Systems, 51-I (12): 2417-2435 (2004)