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Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.

, , , , , , and . DATE, page 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Synthesis of regular computational fabrics with ambipolar CNTFET technology., , , and . ICECS, page 70-73. IEEE, (2010)Towards structured ASICs using polarity-tunable Si nanowire transistors., , , , , , and . DAC, page 123:1-123:4. ACM, (2013)Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors., , , , , , and . NANOARCH, page 55-60. ACM, (2012)Alternative design methodologies for the next generation logic switch., , , and . ICCAD, page 231-234. IEEE Computer Society, (2011)Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology., , , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 6 (3): 339-351 (2016)Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors., , , and . DAC, page 42-47. ACM, (2012)Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs., , , , , , and . DATE, page 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications., , and . NANOARCH, page 65-70. IEEE Computer Society, (2010)