%0 Conference Paper %1 conf/date/GaillardonABMSLM13 %A Gaillardon, Pierre-Emmanuel %A Amarù, Luca Gaetano %A Bobba, Shashikanth %A Marchi, Michele De %A Sacchetto, Davide %A Leblebici, Yusuf %A Micheli, Giovanni De %B DATE %D 2013 %E Macii, Enrico %I EDA Consortium San Jose, CA, USA / ACM DL %K dblp %P 625-630 %T Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs. %U http://dblp.uni-trier.de/db/conf/date/date2013.html#GaillardonABMSLM13 %@ 978-1-4503-2153-2

@inproceedings{conf/date/GaillardonABMSLM13, added-at = {2015-11-11T00:00:00.000+0100}, author = {Gaillardon, Pierre-Emmanuel and Amarù, Luca Gaetano and Bobba, Shashikanth and Marchi, Michele De and Sacchetto, Davide and Leblebici, Yusuf and Micheli, Giovanni De}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/200e8d7392c0dce841c49066876baf13f/dblp}, booktitle = {DATE}, crossref = {conf/date/2013}, editor = {Macii, Enrico}, ee = {http://dl.acm.org/citation.cfm?id=2485442}, interhash = {02003843bcd49ee7b0eea4bc1885637f}, intrahash = {00e8d7392c0dce841c49066876baf13f}, isbn = {978-1-4503-2153-2}, keywords = {dblp}, pages = {625-630}, publisher = {EDA Consortium San Jose, CA, USA / ACM DL}, timestamp = {2016-02-02T13:24:15.000+0100}, title = {Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.}, url = {http://dblp.uni-trier.de/db/conf/date/date2013.html#GaillardonABMSLM13}, year = 2013 }