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High Speed Soft-Error-Tolerant Latch and Flip-Flop Design for Multiple VDD Circuit., , and . ISVLSI, page 273-278. IEEE Computer Society, (2007)Whitespace-aware TSV arrangement in 3D clock tree synthesis., , , , , and . ISVLSI, page 115-120. IEEE Computer Socity, (2013)A low-complexity symbol-level differential detection scheme for IEEE 802.15.4 O-QPSK signals., , , and . WCSP, page 1-6. IEEE, (2012)FPGA and GPU implementation of large scale SpMV., , , , , , and . SASP, page 64-70. IEEE Computer Society, (2010)Application specific sensor node architecture optimization - Experiences from field deployments., , , , , , and . ASP-DAC, page 389-394. IEEE, (2012)HS3DPG: Hierarchical simulation for 3D P/G network., , , , , , and . ASP-DAC, page 509-514. IEEE, (2013)DTW-Based Subsequence Similarity Search on AMD Heterogeneous Computing Platform., , , , , and . HPCC/EUC, page 1054-1063. IEEE, (2013)Modeling of PMOS NBTI Effect Considering Temperature Variation., , , , , and . ISQED, page 139-144. IEEE Computer Society, (2007)TSV-aware topology generation for 3D Clock Tree Synthesis., , , , , , and . ISQED, page 300-307. IEEE, (2013)A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design., , , and . ISQED, page 191-197. IEEE, (2010)