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Whitespace-aware TSV arrangement in 3D clock tree synthesis.

X. Li, W. Liu, H. Du, Y. Wang, Y. Ma, and H. Yang. ISVLSI, page 115-120. IEEE Computer Socity, (2013)

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Di Liu University of Stuttgart

Data for: The silicon vacancy centers in SiC: determination of intrinsic spin dynamics for integrated quantum photonicsD. Liu. Dataset, (2024)Related to: Di Liu, Florian Kaiser, Vladislav Bushmakin, Erik Hesselmeier, Timo Steidl, Takeshi Ohshima, Nguyen Tien Son, Jawad Ul-Hassan, Öney O. Soykal, Jörg Wrachtrup (2023). The silicon vacancy centers in SiC: determination of intrinsic spin dynamics for integrated quantum photonics. arXiv preprint. arXiv: 2307.13648.

Dexing Liu University of Stuttgart

Jan Liu University of Stuttgart

M.Sc. Zhuoran Liu University of Stuttgart

Yanchao Liu University of Stuttgart

Other publications of authors with the same name

Neighborhood Cognition Consistent Multi-Agent Reinforcement Learning.H. Mao, W. Liu, J. Hao, J. Luo, D. Li, Z. Zhang, J. Wang, and Z. Xiao. AAAI, page 7219-7226. AAAI Press, (2020)Neighborhood Cognition Consistent Multi-Agent Reinforcement Learning.H. Mao, W. Liu, J. Hao, J. Luo, D. Li, Z. Zhang, J. Wang, and Z. Xiao. CoRR, (2019)Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis.W. Liu, Y. Wang, G. Chen, Y. Ma, Y. Xie, and H. Yang. IEEE Trans. VLSI Syst., 23 (9): 1842-1853 (2015)On-Chip Hybrid Power Supply System for Wireless Sensor Nodes.W. Liu, Y. Wang, Y. Ma, Y. Xie, and H. Yang. JETC, 10 (3): 23:1-23:22 (2014)Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 12-bit SAR ADC Design Case.W. Liu, G. Chen, X. Han, Y. Wang, Y. Xie, and H. Yang. DAC, page 166:1-166:6. ACM, (2014)Whitespace-aware TSV arrangement in 3D clock tree synthesis.X. Li, W. Liu, H. Du, Y. Wang, Y. Ma, and H. Yang. ISVLSI, page 115-120. IEEE Computer Socity, (2013)TSV-aware topology generation for 3D Clock Tree Synthesis.W. Liu, H. Du, Y. Wang, Y. Ma, Y. Xie, J. Quan, and H. Yang. ISQED, page 300-307. IEEE, (2013)On-chip hybrid power supply system for wireless sensor nodes.W. Liu, Y. Wang, W. Liu, Y. Ma, Y. Xie, and H. Yang. ASP-DAC, page 43-48. IEEE, (2011)Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects.W. Liu, Y. Wang, X. Feng, Y. Huang, H. Yang, Y. Xie, and G. Chen. IEEE Design & Test, 31 (5): 28-35 (2014)Modeling and optimization of low power resonant clock mesh.W. Liu, G. Chen, Y. Wang, and H. Yang. ASP-DAC, page 478-483. IEEE, (2015)