PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Reorda, Matteo Sonza"

Author of the publication

copydeleteadd this publication to your clipboard
A Parallel Tester Architecture for Accelerometer and Gyroscope MEMS Calibration and Test.

, , , , , , , and . J. Electronic Testing, 27 (3): 389-402 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Matteo Schilirò University of Stuttgart

Matteo Bortoletto University of Stuttgart

Matteo Paltenghi University of Stuttgart

 

Other publications of authors with the same name

New Techniques to Reduce the Execution Time of Functional Test Programs., , , and . IEEE Trans. Computers, 66 (7): 1268-1273 (2017)Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug., , , and . IET Computers & Digital Techniques, 4 (2): 104-113 (2010)New techniques for efficiently assessing reliability of SOCs., , , , and . Microelectronics Journal, 34 (1): 53-61 (2003)On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors., , and . IEEE Trans. VLSI Syst., 22 (4): 813-823 (2014)A Flexible Framework for the Automatic Generation of SBST Programs., , , , and . IEEE Trans. VLSI Syst., 24 (10): 3055-3066 (2016)Scan-Chain Intra-Cell Aware Testing., , , , , , and . IEEE Trans. Emerging Topics Comput., 6 (2): 278-287 (2018)GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 15 (8): 991-1000 (1996)A Functional Approach for Testing the Reorder Buffer Memory., , , and . J. Electronic Testing, 30 (4): 469-481 (2014)A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits., , , , , and . J. Electronic Testing, 33 (1): 25-36 (2017)Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs., , , , and . J. Electronic Testing, 23 (1): 47-54 (2007)