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Disambiguation of "Grosso, Michelangelo"

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Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug.

, , , and . IET Computers & Digital Techniques, 4 (2): 104-113 (2010)

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Other publications of authors with the same name

Test Considerations about the Structured ASIC Paradigm., and . DDECS, page 232-233. IEEE Computer Society, (2006)A compact IGBT electro-thermal model in Verilog-A for fast system-level simulation., , , , and . IECON, page 3793-3798. IEEE, (2016)A novel scalable and reconfigurable emulation platform for embedded systems verification., , , , , and . ISCAS, page 865-868. IEEE, (2010)On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores., , , and . European Test Symposium, page 179-184. IEEE Computer Society, (2007)An on-line fault detection technique based on embedded debug features., , , , , and . IOLTS, page 167-172. IEEE Computer Society, (2010)A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions., , , , , and . VTS, page 389-394. IEEE Computer Society, (2008)Addressing the Smart Systems design challenge: The SMAC platform., , , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 39 (8): 1158-1173 (2015)An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs., , , , and . European Test Symposium, page 140-145. IEEE Computer Society, (2008)On the use of embedded debug features for permanent and transient fault resilience in microprocessors., , , , , , and . Microprocessors and Microsystems - Embedded Hardware Design, 36 (5): 334-343 (2012)A SBST strategy to test microprocessors' Branch Target Buffer., , , , and . DDECS, page 306-311. IEEE, (2012)