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A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.

, , , , , and . VTS, page 389-394. IEEE Computer Society, (2008)

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A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions., , , , , and . VTS, page 389-394. IEEE Computer Society, (2008)Towards finding path delay fault tests with high test efficiency using ZBDDs., , and . ICCD, page 464-467. IEEE Computer Society, (2005)Modeling and Analysis of Power-Aware Systems., , , and . TACAS, volume 2619 of Lecture Notes in Computer Science, page 409-425. Springer, (2003)An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration., , and . European Test Symposium, page 141-146. IEEE Computer Society, (2011)Implicit Critical PDF Test Generation with Maximal Test Efficiency., , and . DFT, page 50-58. IEEE Computer Society, (2006)On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation., , and . J. Electronic Testing, 24 (1-3): 203-222 (2008)A Non-Enumerative Technique for Measuring Path Correlation in Digital Circuits., , and . J. Electronic Testing, 28 (6): 843-856 (2012)Identification of critical primitive path delay faults without any path enumeration., , and . VTS, page 9-14. IEEE Computer Society, (2010)Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors., , , , , and . EvoWorkshops, volume 4974 of Lecture Notes in Computer Science, page 224-234. Springer, (2008)Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning., , and . DFT, page 401-409. IEEE Computer Society, (2009)