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Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs.

, and . VLSI Design, page 439-443. IEEE Computer Society, (2014)

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Volume accumulated double gate junctionless MOSFETs for low power logic technology applications., and . ISQED, page 335-340. IEEE, (2014)Back-gate effects and detailed characterization of junctionless transistor., , , , , , , and . ESSDERC, page 282-285. IEEE, (2015)Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory., , , and . VLSI Design, page 422-427. IEEE Computer Society, (2018)Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off., and . IEEE Trans. on Circuits and Systems, 57-I (12): 3048-3054 (2010)Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs., and . SoCC, page 107-110. IEEE, (2009)Investigation of high-performance sub-50 nm junctionless nanowire transistors., , , , , , , and . Microelectronics Reliability, 51 (7): 1166-1171 (2011)Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors., and . VLSI Design, page 168-173. IEEE, (2019)Hysteresis Free sub-60 mV/dec Subthreshold Swing in Junctionless MOSFETs., and . VLSI Design, page 133-138. IEEE Computer Society, (2018)Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs., and . VLSI Design, page 439-443. IEEE Computer Society, (2014)