Author of the publication

Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors.

, and . VLSI Design, page 168-173. IEEE, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Volume accumulated double gate junctionless MOSFETs for low power logic technology applications., and . ISQED, page 335-340. IEEE, (2014)Back-gate effects and detailed characterization of junctionless transistor., , , , , , , and . ESSDERC, page 282-285. IEEE, (2015)Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory., , , and . VLSI Design, page 422-427. IEEE Computer Society, (2018)Improving Operational transconductance Amplifier (OTA) gain-bandwidth tradeoff using gate-underlap MOSFETs., and . SoCC, page 107-110. IEEE, (2009)Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off., and . IEEE Trans. on Circuits and Systems, 57-I (12): 3048-3054 (2010)Investigation of high-performance sub-50 nm junctionless nanowire transistors., , , , , , , and . Microelectronics Reliability, 51 (7): 1166-1171 (2011)Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless Transistors., and . VLSI Design, page 168-173. IEEE, (2019)Hysteresis Free sub-60 mV/dec Subthreshold Swing in Junctionless MOSFETs., and . VLSI Design, page 133-138. IEEE Computer Society, (2018)Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETs., and . VLSI Design, page 439-443. IEEE Computer Society, (2014)