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Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL.

, , and . IWOCL, page 4:1-4:9. ACM, (2014)

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Gzip on a chip: high performance lossless data compression on FPGAs using OpenCL., , and . IWOCL, page 4:1-4:9. ACM, (2014)Bringing programmability to the data plane: Packet processing with a NoC-enhanced FPGA., , and . FPT, page 24-31. IEEE, (2015)Transparent Structural Online Test for Reconfigurable Systems, , , , , , , and . Proceedings of the 18th IEEE International On-Line Testing Symposium (IOLTS'12), page 37--42. IEEE Computer Society, (2012)ShrinkML: End-to-End ASR Model Compression Using Reinforcement Learning., , , , and . CoRR, (2019)The Case for Embedded Networks on Chip on Field-Programmable Gate Arrays., and . IEEE Micro, 34 (1): 80-89 (2014)The power of communication: Energy-efficient NOCS for FPGAS., and . FPL, page 1-8. IEEE, (2013)Take the Highway: Design for Embedded NoCs on FPGAs., , and . FPGA, page 98-107. ACM, (2015)DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration., , , , , , , , , and 1 other author(s). FPL, page 411-418. IEEE Computer Society, (2018)Harnessing Numerical Flexibility for Deep Learning on FPGAs., , , , , , , , , and 1 other author(s). HEART, page 1:1-1:3. ACM, (2018)2.2 GHz LC VCO for RFID on a 0.5-um digital gate-array designed for ultra-thin silicon substrates, , , , , and . German Microwave Conference (GeMiC), page W2-3. Darmstadt, Germany, IEEE, (2011)