Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Verification of CDM circuit simulation using an ESD evaluation circuit., , , , , and . Microelectronics Reliability, 47 (7): 1036-1043 (2007)Substrate potential shift due to parasitic minority carrier injection in smart-power ICs: measurements and full-chip 3D device simulation., , , , and . Microelectronics Reliability, 41 (6): 815-822 (2001)Test circuits for fast and reliable assessment of CDM robustness of I/O stages., , , , , , , , , and . Microelectronics Reliability, 45 (2): 269-277 (2005)Study of CDM specific effects for a smart power input protection structure., , , , , , , , , and . Microelectronics Reliability, 46 (5-6): 666-676 (2006)EMC immunity of integrated smart power transistors in a non-50Ω environment., , and . EMC Compo, page 214-219. IEEE, (2013)Functional analysis of an integrated communication interface during ESD., , , and . EMC Compo, page 125-130. IEEE, (2015)A dual-beam Michelson interferometer for investigation of trigger dynamics in ESD protection devices under very fast TLP stress., , , , , , , , , and . Microelectronics Reliability, 43 (9-11): 1557-1561 (2003)Capacitively coupled transmission line pulsing cc-TLP--a traceable and reproducible stress method in the CDM-domain., , , and . Microelectronics Reliability, 45 (2): 279-285 (2005)