PUMA

academical publication management
collect, organize, and share publications

( en | de )

 

Disambiguation of "Yalamanchili, Sudhakar"

Author of the publication

copydeleteadd this publication to your clipboard
Co-design of multicore architectures and microfluidic cooling for 3D stacked ICs.

, , , and . Microelectronics Journal, 45 (12): 1814-1821 (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

No persons found for author name Yalamanchili, Sudhakar
add a person with the name Yalamanchili, Sudhakar
 

Other publications of authors with the same name

Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture., , , and . J. Parallel Distrib. Comput., 73 (12): 1525-1538 (2013)A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective., , , and . IEEE Trans. VLSI Syst., 19 (5): 809-817 (2011)Augmented Binary Hypercube: A New Architecture for Processor Management., , and . IEEE Trans. Computers, 45 (8): 980-984 (1996)Parallel image normalization on a mesh connected array processor., , and . Pattern Recognition, 20 (1): 115-124 (1987)Interconnection networks - an engineering approach., , and . IEEE, (1997)Formulation of parallel image processing tasks., and . Pattern Recognition Letters, 2 (4): 261-270 (1984)Dynamically Configurable Message Flow Control for Fault-Tolerant Routing., , and . IEEE Trans. Parallel Distrib. Syst., 10 (1): 7-22 (1999)A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks., and . IEEE Trans. Parallel Distrib. Syst., 6 (5): 482-497 (1995)Switching Techniques.. Encyclopedia of Parallel Computing, Springer, (2011)Centralized buffer router: A low latency, low power router for high radix NOCs., and . NOCS, page 1-8. IEEE, (2013)