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Augmented Binary Hypercube: A New Architecture for Processor Management., , and . IEEE Trans. Computers, 45 (8): 980-984 (1996)Design space exploration of on-chip ring interconnection for a CPU-GPU heterogeneous architecture., , , and . J. Parallel Distrib. Comput., 73 (12): 1525-1538 (2013)A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective., , , and . IEEE Trans. VLSI Syst., 19 (5): 809-817 (2011)Dynamically Configurable Message Flow Control for Fault-Tolerant Routing., , and . IEEE Trans. Parallel Distrib. Syst., 10 (1): 7-22 (1999)A Family of Fault-Tolerant Routing Protocols for Direct Multiprocessor Networks., and . IEEE Trans. Parallel Distrib. Syst., 6 (5): 482-497 (1995)Interconnection networks - an engineering approach., , and . IEEE, (1997)Switching Techniques.. Encyclopedia of Parallel Computing, Springer, (2011)Formulation of parallel image processing tasks., and . Pattern Recognition Letters, 2 (4): 261-270 (1984)Centralized buffer router: A low latency, low power router for high radix NOCs., and . NOCS, page 1-8. IEEE, (2013)Parallel image normalization on a mesh connected array processor., , and . Pattern Recognition, 20 (1): 115-124 (1987)