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Bounded Model Checking of Incomplete Real-time Systems Using Quantified SMT Formulas.

, , and . MTV, page 22-27. IEEE Computer Society, (2011)

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On the testability of iterative logic arrays., , , and . Integration, 18 (2-3): 201-218 (1995)Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis., , , , , and . International Journal of Parallel Programming, 38 (3-4): 185-202 (2010)DFG-Projekt RealTest - Test und Zuverlässigkeit nanoelektronischer Systeme (DFG-Project - Test and Reliability of Nano-Electronic Systems)., , , , and . it - Information Technology, 48 (5): 304- (2006)Technische Informatik - eine einführende Darstellung., and . Oldenbourg, (2008)Efficient SAT-Based Circuit Initialization for Larger Designs., , , and . VLSI Design, page 62-67. IEEE Computer Society, (2014)An Analysis Framework for Transient-Error Tolerance., , and . VTS, page 249-255. IEEE Computer Society, (2007)Polynomial Formal Verification of Multipliers., , , , and . VTS, page 150-157. IEEE Computer Society, (1997)The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults., , , , and . VTS, page 171-178. IEEE Computer Society, (2004)An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects., , , , , , and . VTS, page 21-26. IEEE Computer Society, (2009)K*BMDs: A New Data Structure for Verification., , and . ED&TC, page 2-8. IEEE Computer Society, (1996)