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Disambiguation of "Wei, Gu-Yeon"

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SMIV: A 16-nm 25-mm² SoC for IoT With Arm Cortex-A53, eFPGA, and Coherent Accelerators.

, , , , , and . IEEE J. Solid State Circuits, 57 (2): 639-650 (2022)

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Wei Yu University of Stuttgart

Junyuan Gu University of Stuttgart

Dr. rer. nat. Ran Wei University of Stuttgart

Wei Zhang University of Stuttgart

Li-Wei Chen University of Stuttgart

 

Other publications of authors with the same name

Automating Design of Voltage Interpolation to Address Process Variations., , , and . IEEE Trans. VLSI Syst., 19 (3): 383-396 (2011)Pipelined parallel architecture for high throughput MAP detectors., , and . ISCAS (2), page 505-508. IEEE, (2004)Process Variation Tolerant 3T1D-Based Cache Architectures., , , and . MICRO, page 15-26. IEEE Computer Society, (2007)Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling., , , , , , and . MICRO, page 77-88. IEEE Computer Society, (2010)Digital wireline and PLL techniques., and . CICC, IEEE, (2009)A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction., , and . CICC, page 459-462. IEEE, (2008)DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications., , , and . J. Solid-State Circuits, 53 (9): 2722-2731 (2018)A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance., , , and . J. Solid-State Circuits, 43 (4): 855-863 (2008)An 8×5 Gb/s Parallel Receiver With Collaborative Timing Recovery., , , and . J. Solid-State Circuits, 44 (11): 3120-3130 (2009)Network Pruning for Low-Rank Binary Indexing., , , , and . CoRR, (2019)