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A light-weight Network-on-Chip architecture for dynamically reconfigurable systems.

, , , and . ICSAMOS, page 49-56. IEEE, (2008)

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Data Path Testability Analysis Based on BDDs., , and . ISCAS, page 2012-2014. IEEE, (1995)GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications., , and . ISCAS, page 912-915. IEEE, (1995)Two-Dimensional Sequential Array Architectures: Design for Testability Approaches., , and . ISCAS, page 81-84. IEEE, (1994)An Output/State Encoding for Self-Checking Finite State Machine., and . ISCAS, page 2136-2139. IEEE, (1995)Experimental Evaluation and Modeling of Thermal Phenomena on Mobile Devices., , , , and . DSD, page 306-313. IEEE Computer Society, (2015)Efficient Hardware Design of Iterative Stencil Loops., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 35 (12): 2018-2031 (2016)Co-synthesis and co-simulation of control-dominated embedded systems., , and . Design Autom. for Emb. Sys., 1 (3): 257-289 (1996)Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms., , , , , , and . TRETS, 4 (3): 29:1-29:22 (2011)Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration., , , , , and . IEEE Trans. VLSI Syst., 17 (11): 1650-1654 (2009)ReBit: A Tool to Manage and Analyse FPGA-Based Reconfigurable Systems., , , and . IPDPS Workshops, page 220-227. IEEE, (2011)