%0 Journal Article %1 journals/tcad/RanaBBNAS16 %A Rana, Vincenzo %A Beretta, Ivan %A Bruschi, Francesco %A Nacci, Alessandro Antonio %A Atienza, David %A Sciuto, Donatella %D 2016 %J IEEE Trans. on CAD of Integrated Circuits and Systems %K dblp %N 12 %P 2018-2031 %T Efficient Hardware Design of Iterative Stencil Loops. %U http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#RanaBBNAS16 %V 35

@article{journals/tcad/RanaBBNAS16, added-at = {2016-11-25T00:00:00.000+0100}, author = {Rana, Vincenzo and Beretta, Ivan and Bruschi, Francesco and Nacci, Alessandro Antonio and Atienza, David and Sciuto, Donatella}, biburl = {https://puma.ub.uni-stuttgart.de/bibtex/24b03ce1bee6f6046f8f2dd2a74b51cc8/dblp}, ee = {http://dx.doi.org/10.1109/TCAD.2016.2545408}, interhash = {eca2366f7ab37f0c79c80b36685fc45d}, intrahash = {4b03ce1bee6f6046f8f2dd2a74b51cc8}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, keywords = {dblp}, number = 12, pages = {2018-2031}, timestamp = {2016-11-26T10:32:44.000+0100}, title = {Efficient Hardware Design of Iterative Stencil Loops.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad35.html#RanaBBNAS16}, volume = 35, year = 2016 }