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A light-weight Network-on-Chip architecture for dynamically reconfigurable systems.

, , , and . ICSAMOS, page 49-56. IEEE, (2008)

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SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture., , , and . ERSA, page 63-69. CSREA Press, (2006)Adaptive Raytracing Implementation Using Partial Dynamic Reconfiguration., , , , , and . IPDPS Workshops, page 236-242. IEEE Computer Society, (2014)A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures., , , and . ReConFig, page 1-6. IEEE, (2015)EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing., , , , , , , , , and 7 other author(s). CSE, page 339-342. IEEE Computer Society, (2015)An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures., , and . Int. J. Reconfig. Comp., (2009)Scala-Based Domain-Specific Language for Creating Accelerator-Based SoCs., , , and . IPDPS Workshops, page 225-232. IEEE Computer Society, (2016)Hardware Design Automation of Convolutional Neural Networks., , , , , and . ISVLSI, page 224-229. IEEE Computer Society, (2016)FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration., , , , , , , , , and 11 other author(s). Microprocessors and Microsystems - Embedded Hardware Design, 39 (4-5): 321-338 (2015)Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs., , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 28 (5): 662-675 (2009)SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures., , , , , , , , , and . ARC, volume 8405 of Lecture Notes in Computer Science, page 337-344. Springer, (2014)