Author of the publication

High-Level Synthesis for FPGAs: From Prototyping to Deployment.

, , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (4): 473-491 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization., , , , , , and . FCCM, page 231-234. IEEE Computer Society, (2009)Multithreaded pipeline synthesis for data-parallel kernels., , , and . ICCAD, page 718-725. IEEE, (2014)Characterizing the Benefits and Limitations of Smart Building Meeting Room Scheduling., , and . ICCPS, page 6:1-6:10. IEEE Computer Society, (2016)Building Efficient Deep Neural Networks with Unitary Group Convolutions., , , , and . CoRR, (2018)Channel Gating Neural Networks., , , and . CoRR, (2018)Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs., , , , , and . IET Cyper-Phys. Syst.: Theory & Appl., 1 (1): 70-77 (2016)Bit-level optimization for high-level synthesis and FPGA-based acceleration., , , , , , and . FPGA, page 59-68. ACM, (2010)T2S-Tensor: Productively Generating High-Performance Spatial Hardware for Dense Tensor Computations., , , , , , , , , and 5 other author(s). FCCM, page 181-189. IEEE, (2019)Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set Specifications., , and . DAC, page 122. ACM, (2019)Reverse engineering convolutional neural networks through side-channel information leaks., , and . DAC, page 4:1-4:6. ACM, (2018)