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Bus encoding for total power reduction using a leakage-aware buffer configuration., , , and . IEEE Trans. VLSI Syst., 13 (12): 1376-1383 (2005)Circuit optimization techniques to mitigate the effects of soft errors in combinational logic., , , and . ACM Trans. Design Autom. Electr. Syst., 15 (1): 5:1-5:27 (2009)Modeling and Analysis of Parametric Yield under Power and Performance Constraints., , , and . IEEE Design & Test of Computers, 22 (4): 376-385 (2005)Statistical estimation of leakage current considering inter- and intra-die process variation., , , and . ISLPED, page 84-89. ACM, (2003)IBM POWER7+ design for higher frequency at fixed power., , , , , , , , and . IBM Journal of Research and Development, (2013)Soft error reduction in combinational logic using gate resizing and flipflop selection., , and . ICCAD, page 502-509. ACM, (2006)Analytical yield prediction considering leakage/performance correlation., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (9): 1685-1695 (2006)An efficient surface-based low-power buffer insertion algorithm., , , , and . ISPD, page 86-93. ACM, (2005)Parametric yield estimation considering leakage variability., , , and . DAC, page 442-447. ACM, (2004)Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors., , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 26 (3): 468-479 (2007)