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Cross-Layer Modeling and Simulation of Circuit Reliability.

Y. Cao, J. Velamala, K. Sutaria, M. Chen, J. Ahlbin, I. Esqueda, M. Bajura, and M. Fritze. IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (1): 8-23 (2014)

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Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging.E. Mintarno, J. Skaf, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R. Dutton, and S. Mitra. IEEE Trans. on CAD of Integrated Circuits and Systems, 30 (5): 760-773 (2011)Optimized self-tuning for circuit aging.E. Mintarno, J. Skaf, R. Zheng, J. Velamala, Y. Cao, S. Boyd, R. Dutton, and S. Mitra. DATE, page 586-591. IEEE, (2010)Circuit aging prediction for low-power operation.R. Zheng, J. Velamala, V. Reddy, V. Balakrishnan, E. Mintarno, S. Mitra, S. Krishnan, and Y. Cao. CICC, page 427-430. IEEE, (2009)A self-tuning design methodology for power-efficient multi-core systems.J. Sun, R. Zheng, J. Velamala, Y. Cao, R. Lysecky, K. Shankar, and J. Roveda. ACM Trans. Design Autom. Electr. Syst., 18 (1): 4:1-4:24 (2012)Cross-Layer Modeling and Simulation of Circuit Reliability.Y. Cao, J. Velamala, K. Sutaria, M. Chen, J. Ahlbin, I. Esqueda, M. Bajura, and M. Fritze. IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (1): 8-23 (2014)Statistical aging under dynamic voltage scaling: A logarithmic model approach.J. Velamala, K. Sutaria, H. Shimizu, H. Awano, T. Sato, and Y. Cao. CICC, page 1-4. IEEE, (2012)A self-evolving design methodology for power efficient multi-core systems.J. Sun, R. Zheng, J. Velamala, Y. Cao, R. Lysecky, K. Shankar, and J. Roveda. ICCAD, page 264-268. IEEE, (2010)Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets.N. Seifert, S. Jahinuzzaman, J. Velamala, and N. Patel. IRPS, page 2. IEEE, (2015)Design sensitivity of single event transients in scaled logic circuits.J. Velamala, R. LiVolsi, M. Torres, and Y. Cao. DAC, page 694-699. ACM, (2011)Circuit-level delay modeling considering both TDDB and NBTI.H. Luo, X. Chen, J. Velamala, Y. Wang, Y. Cao, V. Chandra, Y. Ma, and H. Yang. ISQED, page 14-21. IEEE, (2011)

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Cross-Layer Modeling and Simulation of Circuit Reliability.

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Disambiguation of "Velamala, Jyothi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Cross-Layer Modeling and Simulation of Circuit Reliability.

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Cross-Layer Modeling and Simulation of Circuit Reliability.