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Disambiguation of "Chen, Mike Shuo-Wei"

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Cross-Layer Modeling and Simulation of Circuit Reliability.

, , , , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 33 (1): 8-23 (2014)

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Li-Wei Chen University of Stuttgart

Wei Yu University of Stuttgart

Mike Söhner University of Stuttgart

Shuo Wang University of Stuttgart

Mike Kornely University of Stuttgart

 

Other publications of authors with the same name

A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS., , and . CICC, page 1-4. IEEE, (2013)Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications., , , , , and . ICC, page 5769-5774. IEEE, (2007)27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS., and . ISSCC, page 456-457. IEEE, (2016)A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS., and . J. Solid-State Circuits, 51 (12): 3216-3230 (2016)Design and implementation of a CMO 802.11n SoC., , , , , , , , , and 18 other author(s). IEEE Communications Magazine, 47 (4): 134-143 (2009)Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems., , , , , and . EURASIP J. Wireless Comm. and Networking, (2006)A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer., and . J. Solid-State Circuits, 55 (3): 557-566 (2020)A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling., and . IEICE Transactions, 88-C (6): 1114-1121 (2005)A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS., and . CICC, page 1-4. IEEE, (2013)A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS., , , and . VLSIC, page 1-2. IEEE, (2014)