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Disambiguation of "Maurine, Philippe"

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, , , and . CS2@HiPEAC, page 35-38. ACM, (2015)

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Jun. -Prof. Dr. Philippe Grönquist University of Stuttgart

 

Other publications of authors with the same name

Gate Sizing for Low Power Design., , and . VLSI-SOC, volume 218 of IFIP Conference Proceedings, page 301-312. Kluwer, (2001)Statistical timing characterization., , , and . ISSoC, page 1-4. IEEE, (2012)Logical effort model extension to propagation delay representation., , , , , and . IEEE Trans. on CAD of Integrated Circuits and Systems, 25 (9): 1677-1684 (2006)Circuit sizing method under delay constraint., , , and . ISCAS, IEEE, (2006)Security evaluation of dual rail logic against DPA attacks., , , and . VLSI-SoC, page 181-186. IEEE, (2006)A model of the leakage in the frequency domain and its application to CPA and DPA., , , , and . J. Cryptographic Engineering, 4 (3): 197-212 (2014)Voltage Spikes on the Substrate to Obtain Timing Faults., , , , and . DSD, page 483-486. IEEE Computer Society, (2013)Techniques for EM Fault Injection: Equipments and Experimental Results.. FDTC, page 3-4. IEEE Computer Society, (2012)Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier., , , , , , and . ISVLSI, page 316-321. IEEE Computer Society, (2008)Performance Metric Based Optimization Protocol., , , , and . PATMOS, volume 3254 of Lecture Notes in Computer Science, page 100-109. Springer, (2004)