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Compact and Secured Primitives for the Design of Asynchronous Circuits., , and . J. Low Power Electronics, 1 (1): 20-26 (2005)Improvement of dual rail logic as a countermeasure against DPA., , and . VLSI-SoC, page 270-275. IEEE, (2007)A Novel Asynchronous e-FPGA Architecture for Security Applications., , , , , , , and . FPT, page 369-372. IEEE, (2007)Security evaluation of dual rail logic against DPA attacks., , , and . VLSI-SoC, page 181-186. IEEE, (2006)A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates., and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 394-403. Springer, (2007)Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA., , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 340-351. Springer, (2007)A Reconfigurable Cell for a Multi-Style Asynchronous FPGA., , , , , and . ReCoSoC, page 15-22. Univ. Montpellier II, (2007)Physical Design of FPGA Interconnect to Prevent Information Leakage., , , , , , , and . ARC, volume 4943 of Lecture Notes in Computer Science, page 87-98. Springer, (2008)A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback, , , , , , , and . CoRR, (2011)A Method to Design Compact Dual-rail Asynchronous Primitives., , , and . PATMOS, volume 3728 of Lecture Notes in Computer Science, page 571-580. Springer, (2005)